Path: utzoo!mnetor!uunet!lll-winken!lll-tis!ames!amdahl!pyramid!voder!apple!bcase
From: bcase@Apple.COM (Brian Case)
Newsgroups: comp.arch
Subject: Re: RISC != real-time control
Message-ID: <9308@apple.Apple.Com>
Date: 3 May 88 17:49:51 GMT
References: <1521@pt.cs.cmu.edu> <1532@pt.cs.cmu.edu> <476@pcrat.UUCP> <833@imagine.PAWL.RPI.EDU>
Reply-To: bcase@apple.UUCP (Brian Case)
Organization: Apple Computer Inc, Cupertino, CA
Lines: 19
Keywords: RISC, real-time

In article <833@imagine.PAWL.RPI.EDU> jesup@pawl18.pawl.rpi.edu (Randell E. Jesup) writes:
=	Yeah, and what technology is this wonder-chip implemented in???
=Whatever it is, I can think of dozens of Si companies that would give away
=all their current facilites for that process.  Oh, and I'm not even worrying
=about cost.
=
=	Back to reality, it just can't be done, except MAYBE with a state of
=the art chip optimized to NOTHING but fast dhrystones (which, by the way,
=are a pretty poor predicter for most applications, due to string handling.)
=4 Mhz is REAL slow.  A 4Mhz rpm-40 would be equivalent to maybe a 14Mhz
=68000 (note: not '020).  At such slow speeds, CISC chips may well show
=superiority due to wanting to maximize the usefulness of every bus cycle.

On the contrary.  Let me say it again:  the ARM from VTI and ACORN.  At low
clock rates (so that memory access time isn't an issue), the ARM gets about
1K dhrystones per MHz (using the rather decent ACORN C compiler).  The
process is (was) junky 2 or 3 micron CMOS.  Current price for the ARM
(VTI 86000 I think is the part number) is very low in quantity, < $15 I
think.  The only problem for meeting the original poster's requirements is
the 32-bit bus of the ARM.