Path: utzoo!mnetor!uunet!lll-winken!lll-tis!mordor!sri-spam!sri-unix!garth!walter
From: walter@garth.UUCP (Walter Bays)
Newsgroups: comp.arch
Subject: Re: SPARC and multiprocessing
Message-ID: <627@garth.UUCP>
Date: 3 May 88 18:26:19 GMT
References: <1521@pt.cs.cmu.edu> <28200135@urbsdc> <4921@bloom-beacon.MIT.EDU> <1671@alliant.Alliant.COM> <623@garth.UUCP> <1699@alliant.Alliant.COM>
Reply-To: walter@garth.UUCP (Walter Bays)
Organization: INTERGRAPH (APD) -- Palo Alto, CA
Lines: 23

>>In article <1671@alliant.Alliant.COM> jeff@alliant.UUCP (Jeff Collins) writes:
>>>	Given that the SPARC must use a virtual cache to get optimal
>>>	performance, how does one build a multiprocessor with a SPARC?
>>>	As far as I know, no one has solved the virtual cache coherency
>>>	problem yet...

>>[I replied about 'bus watch' citing Clipper and 88000.]

In article <1699@alliant.Alliant.COM> jeff@alliant.UUCP (Jeff Collins) writes:
>	Actually I am familiar with the Clipper and the 88000.  I know how they
>	support multiprocessing.  The point here was that these chips put the
>	cache after the MMU.  [Good description of the problems in 'bus
>	watching' with virtual caches.]

You're right.  I missed your point.  Clipper has a physical cache, while
the Sun 4 SPARC has a virtual cache.
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