Path: utzoo!mnetor!uunet!steinmetz!davidsen
From: davidsen@steinmetz.ge.com (William E. Davidsen Jr)
Newsgroups: comp.arch
Subject: Re: Do RISC Compilers Consider Multiprogramming?
Message-ID: <10707@steinmetz.ge.com>
Date: 4 May 88 12:17:08 GMT
References: <620@speedy.mcnc.org>
Reply-To: davidsen@crdos1.UUCP (bill davidsen)
Organization: General Electric CRD, Schenectady, NY
Lines: 16
Keywords: RISC compiler context-switch architecture multiprogramming

[ discussion of generating a good compiler which preserves state in a
  multi processor environment ]
   
  Interesting thought from the past... the GE 600 series allowed
interrupts on an instruction fetch from an even location (since the bus
was 72 bits wide that was every other instruction). This resulted in the
ability to preserve context throught a few instructions.

  What are the ramification of doing the same thing on a newer
processor? If you knew that you could keep all the balls in the air for
two (or 2^N) instructions could you write a better compiler? Would a half
instruction increase in interrupt latency affect thruput adversely?
-- 
	bill davidsen		(wedu@ge-crd.arpa)
  {uunet | philabs | seismo}!steinmetz!crdos1!davidsen
"Stupidity, like virtue, is its own reward" -me