Path: utzoo!mnetor!uunet!lll-winken!lll-crg.llnl.gov!brooks
From: brooks@lll-crg.llnl.gov (Eugene D. Brooks III)
Newsgroups: comp.arch
Subject: Re: The WM Machine
Message-ID: <6762@lll-winken.llnl.gov>
Date: 5 May 88 04:22:52 GMT
References: <5339@aw.sei.cmu.edu>
Sender: usenet@lll-winken.llnl.gov
Reply-To: brooks@lll-crg.llnl.gov.UUCP (Eugene D. Brooks III)
Organization: Lawrence Livermore National Laboratory
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I thought I would add a little technical support to a couple of the points.

In article <5339@aw.sei.cmu.edu> firth@sei.cmu.edu (Robert Firth) writes:
>In sum, I believe the use of FIFOs offers no advantages over loads and
>stores into and out of the general registers, and incurs several
>disadvantages.
Also, the fifo that results of load requests return to in general will
have to sort the data that arrives so that any scrambling of arrival
order, which is very frequent in a multiprocessor, is fixed up.  The
internal structure used to do this looketh very much like registers,
so why not just stay with registers!
>
>. the machine is crippled by inadequate addressing capability
No scatter/gather capability for vectors, something that has become
very popular on supercomputers, with good reason.