Path: utzoo!mnetor!uunet!ccicpg!leo!jack From: jack@leo.UUCP ( Jack Benkual) Newsgroups: comp.arch Subject: CCI's new RISC-based system Message-ID: <3035@leo.UUCP> Date: 5 May 88 01:03:12 GMT Organization: CCI CPD (Advanced Development), Irvine CA Lines: 216 Since CCI does not get as much press coverage as other manufacturers, I am posting the press release annoncing our new RISC based system. This is mostly marketing data but I will be happy to clarify any technical issues. There are few technical articles published in ICCD-87 and COMPCON-88. CCI UNVEILS BREAKTHROUGH IN RISC ARCHITECTURE CHIP SET; NEW PROCESSORS TO BE INTEGRATED INTO PLANNED FAMILY OF NEW HIGH-PERFORMANCE UNIX*-BASED SUPER-MINICOMPUTERS WITH SUN SPARC STANDARD COMPATIBILITY Irvine, CA--April 25, 1988--The Computer Products Division (CPD) of Computer Consoles, Inc. (CCI) today announced its plans for a new series of super-minicomputers called the CCI POWER 7/64. The new processors, which will be based on a new reduced instruction set computing (RISC) architecture chip set developed by CCI engineers, will deliver 40 million instructions per second (MIPS) of peak performance and 25 MIPS of sustained performance. The new CCI chip set has been specifically designed and optimized for the UNIX environment. The planned series of new processors and systems, which will be introduced in late 1988, will enable CCI customers to run Sun SPARC (ABI) application programs. "Recent market announcements have prompted requests from our customers for more details on our RISC development efforts," said John F. Cunningham, chairman and CEO of CCI. "We believe we are further down the design road than others who have already announced products or strategies, and that our design evolution is mature enough to warrant a public announcement." The result of a three-year, $20 million development effort, "the new chip set and resultant systems will let us achieve never-before realized processing speeds at a price point never before attainable," Cunningham added. DESIGN TECHNOLOGY The new CCI chip set incorporates an instruction processor chip; a bus switch chip; and interfaces to industry-standard floating point arithmetic processor chips. The two CCI-designed chips are being fabricated by Performance Semiconductor of Sunnyvale, Calif., using a 1.2 micron complementary metal-oxide semiconductor (CMOS). CCI engineers have developed very precise and accurate design simulation tools for the development of the new RISC architecture chip sets. "The tools have worked so well that the bus chip came back from the foundry and worked at full speed on the first pass," noted Harold Koplow, senior vice president and chief development officer of CCI. Koplow added, "We've been able to achieve tremendous performance breakthroughs with several unique architectural innovations in our chip set design made possible, in part, by packing 560,000 devices on a single chip. CCI innovations include reduced instruction set concepts coupled with very large scale integration (VLSI) designs; on-chip instruction and data cache techniques; increased processing bandwidths; simpler and shorter instruction pipelines; wider horizontal instruction words; and a unique support of fast call and return instructions." Koplow also noted that the company has applied for patents on its chip set design. In addition, the company's chip set design supports extremely fast processor cycle time. The first CCI POWER 7/64 systems are expected to have a shorter processor cycle time (20 nanoseconds) than recently introduced systems from other manufacturers, and cycle times are expected to become even shorter with future product updates. Design and architecture features developed by CCI engineers that enable the planned CCI POWER 7/64 systems to reach 40 MIPS of peak performance per processor include: RISC Architecture RISC concepts and other unique architectural features allow for an optimal use of custom CMOS very large scale integration (VLSI) chip design. CCI laboratory-conducted simulations have shown future versions of the chip set that are capable of delivering performance up to 70 MIPS per processor without major changes to the current design. Subsequent designs based on one micron and submicron CMOS will increase performance even more. On-Chip Cache Advances in circuit technology that allow larger caches have enabled CCI to design its chip set with a fully integrated cache. CCI's on-chip cache design limits the need for the slower off-chip memory access required by other designs, reduces cache access time and allows for wider data paths than Berkeley RISC, Sun SPARC or other competitive systems. Bandwidth Support For Increased Computer Performance The CCI chip-set has several unique features to deliver the high bandwidth required by short processor time and reduced cycle time, including: 512-bit internal data paths to on-chip cache, bus switch chip memory interface support, 256-bit block transfers to on-board memory, and a high performance 64-bit system bus interface to other processors and I/O controllers. Simpler And Shorter Instruction Pipeline Unlike other RISC implementations that rely on long pipelines and less concurrency to shorten cycle times, CCI's RISC chip set incorporates a simple three-stage pipeline: Stage 1 - Instruction fetch Stage 2 - Instruction execution Stage 3 - Register file write completion The pipeline is handled by hardware so less burden is placed on the compilers than in most other RISC architectures. Horizontal Instruction Word CCI chip set instructions are 64 bits wide and have one fixed format. All instructions are composed of branch control fields, execution control fields and a 32-bit literal. This design results in fast instruction decoding, branch and execution operations performed in parallel from one instruction, and simple address modes. The high level of concurrency offered by CCI's compiler optimization technique is simpler and more effective than management of a long, exposed pipeline, as found in other RISC implementations. Unique Support For Call And Return Because of its internal cache design, the CCI chip set can incorporate a small, fast register file containing 32 (thirty-two) 32-bit general-purpose registers. Through a unique implementation of a 512-bit path between cache and the register file, call and return functions execute in one cache cycle as do most other machine instructions. PROCESSOR PERFORMANCE Based on the new chip set design, CCI's new POWER 7/64 systems are expected to offer sustained performance of 25 MIPS on processor running native UNIX applications. This is more than three times faster than the recently announced Sun SPARC system and four to six times faster than the highest performance Digital Equipment Corporation (DEC) single processor, the VAX 8700. Multi-processor configurations are also planned that will offer even higher performance ratings. The CCI processor implementation will be on a single board (including up to 64 MB of memory), allowing the systems to be priced substantially less than the DEC VAX 8000 series, an industry benchmark for price/performance. By implementing a compatibility strategy, the CCI POWER 7/64 will be able to run Sun SPARC applications significantly faster than the Sun 4/260. "This SPARC compatibility strategy allows our customers to have both a pure performance engine for native UNIX environments at up to 40 MIPS and a means of running their ABI applications," added Joe Perry, vice president of sales and marketing for CPD. SOFTWARE The new CCI POWER 7/64 systems will be source compatible with the existing CCI POWER 6/32 and provide a smooth upgrade path when higher performance is needed. A rich portfolio of software for the CCI POWER 7/64 is made possible by its support of UNIX V, SPARC ABI compatibility and CCI POWER 6/32 compatibility. To support early development of new applications, a full complement of CCI POWER 7/64 third-party software development tools will be available on the CCI POWER 6/32 in June of 1988. The POWER 6/32 is currently integrated into the product lines of ICL Computers and UNISYS as their midrange and high-end UNIX engines. "With an architecture that will accommodate up to four CPUs reaching peak performance of 100 MIPS and more--and a full array of operating systems and networking, communications--and application software offerings at the time of introduction, we believe CCI is setting a new price/performance point for the industry," added N. D'Arcy Roche, senior vice president and general manager of the Computer Products Division of CCI. "The CCI RISC architecture chip set being incorporated into our new CCI POWER 7/64 systems is a natural extension of our five- year history of delivering high-performance, super-minicomputer systems that are optimized for UNIX environments. Our present systems, the CCI POWER 6/32 series, reaches speeds of up to 15 MIPS and incorporates a wide array of systems and applications software, as well as peripherals and networking options. Our announcement today builds on that tradition," Roche said. Cunningham added, "The new RISC architecture chip set and planned CCI POWER 7/64 super-minicomputer family are the single most important new product developments in our company's history. We are coming off a record-setting year, and these new products will position us for continued growth in the 1990s." Headquartered in Waltham, Mass., CCI develops and manufactures super-minicomputer systems in Irvine, Calif., communications systems in Rochester, N.Y., and integrated OFFICEPOWER software in Reston, Va. CCI's common stock is traded on the American Stock Exchange under the ticker symbol CCS. * * * UNIX is a registered trademark of AT & T. SPARC is a trademark of Sun Microsystems, Inc. -- Simplify! Simplify! Simplify! | jack Benkual @ uunet!ccicpg!leo!jack | CCI Computers (nee Computer Consoles Inc)