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From: lindsay@k.gp.cs.cmu.edu (Donald Lindsay)
Newsgroups: comp.arch
Subject: Re: virtual cache coherency
Message-ID: <1605@pt.cs.cmu.edu>
Date: 5 May 88 04:23:49 GMT
Sender: netnews@pt.cs.cmu.edu
Organization: Carnegie-Mellon University, CS/RI
Lines: 23

Actually, there is a trivial way to keep virtual caches coherent.  Just
widen the address bus, so that the virtual address is transmitted along
with the physical address.

This may sound pretty silly, since it costs perhaps 32 extra signals.  (A
page number is about 20, plus you need to identify the address space.)
However, three comments:

- the extra signals don't actually go to memory: they are an
  "inter-processor coherency bus". If all the processors are on the same
  circuit board, this could actually be a good way to go.

- if the OS keeps one physical address at multiple virtual addresses, then
  this scheme is still no worse than other schemes.

- if IO devices generate physical addresses (only), then reverse-mapping
  schemes have the advantage.

Which brings up the question, why don't we do IO with virtual addresses? 
We have living proof that it can be done. Why isn't it catching on?

-- 
	Don		lindsay@k.gp.cs.cmu.edu    CMU Computer Science