Path: utzoo!mnetor!uunet!mcvax!ukc!reading!onion!cf-cm!mch From: mch@computing-maths.cardiff.ac.uk (Major Kano) Newsgroups: comp.arch Subject: Is the Intel memory model safe from NO-ONE ?!? Message-ID: <353@cf-cm.UUCP> Date: 3 May 88 18:06:34 GMT References: <1806@obiwan.mips.COM> <2904@omepd> Reply-To: mch@computing-maths.cardiff.ac.uk (Major Kano) Followup-To: comp.arch Organization: University College Cardiff, Wales, United Kingdom Lines: 89 Keywords: 386 intel memory protection management model segmented Summary: The Intel Strikes Back (well it doesn't, so I will.) This is a partial reprint of an article that I posted in mid March. Please read it carefully as only one person replied last time; and I'd like to comment on this subject and invite others to. -------------------------------------------------------------------------------- In article <2904@omepd> mcg@iwarpo3.UUCP (Steve McGeady) writes: > >It can't be elegance of design, for (e.g.) the 80386 and the MIPSco processor >are each somewhat inelegant in their own ways (for those who don't wish to >fill in the blanks, segmentation and register model in the former case, ^^^^^^^^^^^^ ^^^^^ ** WHAT THE $@#@++%%& HELL ?!? ** Wow ! And I thought Ray Coles (writes for Practical Computing, a UK Magazine) had it in for Intel ! Agreeing, as I do, that the register model doesn't have enough of them, and that even the '386 isn't regular enough, I though that the feature of the '386 that made it so TECHNICALLY advanced (IBM compatibility not withstanding :-) ** WAS ** its memory management and protection model. The 32-bit within-segment addresses are what people have been waiting for for ages. I would question the fact that only 16 bit selectors are avaliable, but I defy anyone to come up, in the near or intermediate future, with an Intel-style memory model that is better than Intel's, without opening up a whole can of voracious memory-eating killer-worms at the descriptor table level. If you don't know what I mean by that, pretend for a moment, that YOU were the person who had to come up with the byte/page granularity kludge in order to make 4GB segments fit in a DT entry. [ Perhaps that person (or team) would like to comment themselves, if they use the net. I would be interested as to what choices they started out with, before deciding on this and why they decided on it. ] What does everyone think ? As a computer architecture junkie, I would be very interested, as the Intel segments seem (to me) to come in for a lot of flack every so often; I just didn't expect it to come from an Intel employee. [1] *) -------------------------------------------------------------------------------- [1] The original poster has already replied (on the net) to this point. -------------------------------------------------------------------------------- In e-mail to me, someone (who since it was e-mail, I will not name without his permission -- thanks for writing, by the way) wrote the following:-- >I happen to agree with you -- I LIKE the basic Intel memory architecture. >It's more open to the future than the motorola 32-bit addresses. I think >we're heading into the world of 32-bit physical address spaces soon, and I >think that the segmented architecture is the right way to go. Apparently, >nobody else (who matters) does, though. I find the segmented architecture is a natural way of protecting programs and data, and although we often hear negative remarks, no-one seems to be able to give any coherent justification of such remarks. In particular. no-one has EVER in my experience directly compared segmenting to straight linear/paging without TOTALLY ignoring the advantages of segmenting, ie., ease of doing relocatable code, logical program design (code, data/heap stack separation), inter-task separation (LDT's) and a few other related features. (As an aside, I've heard of 68000 routines doing all kinds of contortions to check for/avoid overflow because the 68K traps on (eg., zerodivide) and traps into SUPERVISOR mode (believe it or not). Zerodivide should normally be a USER (ie., compiler's run time system) problem. With Intel, the user can handle it without compromising security (conforming code segments). With the 68K you get NO choice. Any 68K programmers out there who can confirm or deny this ? I am referring to articles in the "SUBSET" feature of Personal Computer World about a year and a half ago. I can't remember exactly which issues). I would like, provided people can temporarily dispense with the apathy that ensured that I only got one reply to my original posting, to hear a wide range of views about this. I'm sure there must be people on the net who would like to express opinions or read those of others. So how about it ? This issue has been a bone of contention among computerists for years; surely comp.arch is the very place in which it should be discussed. -mch -- Martin C. Howe, University College Cardiff | "You actually program in 'C' mch@vax1.computing-maths.cardiff.ac.uk. | WITHOUT regular eye-tests ?!" -------------------------------------------+-----+------------------------------ My cats know more about UCC's opinions than I do.| MOSH! In the name of ANTHRAX!