Path: utzoo!mnetor!uunet!husc6!bloom-beacon!tut.cis.ohio-state.edu!mailrus!nrl-cmf!ames!lamaster
From: lamaster@ames.arpa (Hugh LaMaster)
Newsgroups: comp.arch
Subject: Re: RISC  a short answer??
Message-ID: <8333@ames.arpa>
Date: 5 May 88 17:16:02 GMT
References: <1036@nusdhub.UUCP> <1988May3.224604.2252@utzoo.uucp> <383@m3.mfci.UUCP> <770@l.cc.purdue.edu>
Reply-To: lamaster@ames.arc.nasa.gov.UUCP (Hugh LaMaster)
Organization: NASA Ames Research Center, Moffett Field, Calif.
Lines: 31

In article <770@l.cc.purdue.edu> cik@l.cc.purdue.edu (Herman Rubin) writes:
>
>The philosophy of RISC seems to be, to quote one of the above articles, that
>one shoul not worry about the "slow" instructions to speed up 70% of the 

"RISC" has become a generic term for any machine that is optimized for having
the fastest possible processor given all the other constraints.  

It is difficult to remember back to those early years, say ten years ago,
when the VAX processor family was in its adolescence, but, a major selling
point of VAXes was that the code was very compact.  That was very important
then because:
1) Processor real estate was expensive
2) Memory was expensive
3) Memory was slow

The CDC 7600 was a ~20MIPS (780=1), 3MFLOPS machine with a two level memory
of 64K (60 bit words) and 512K (likewise): you could call it ~4 MBytes for
the purposes of comparison.  That was a LOT of memory for its day.
1 MIPS processors of the early 70's had about 1 MB of memory. 

Since then, design constraints have changed and code compactness is not a
major selling point.  Possibly, in the future, it may again become so,
increasing the advantages of CISC type instruction sets (e.g. VAX).

As for the specific architectural features of some of the early "RISC"
processors - I still think that register windows are a poor design 
choice in most cases.  It is surprising to me that they are so popular,
.  I wish that the chip real estate devoted to register windows would
be devoted to a smaller number (32 say) all purpose 64 bit registers
with better floating point support.