Path: utzoo!mnetor!uunet!husc6!bloom-beacon!gatech!udel!princeton!phoenix!pupthy2!lgy
From: lgy@pupthy2.PRINCETON.EDU (Larry Yaffe)
Newsgroups: comp.arch
Subject: Re: RISC  a short answer??
Message-ID: <2792@phoenix.Princeton.EDU>
Date: 5 May 88 22:22:08 GMT
References: <1036@nusdhub.UUCP> <1988May3.224604.2252@utzoo.uucp> <383@m3.mfci.UUCP> <770@l.cc.purdue.edu> <8333@ames.arpa>
Sender: news@phoenix.Princeton.EDU
Reply-To: lgy@pupthy2.PRINCETON.EDU (Larry Yaffe)
Organization: Physics Dept, Princeton Univ
Lines: 15

In article <8333@ames.arpa> lamaster@ames.arc.nasa.gov.UUCP (Hugh LaMaster) writes:
>As for the specific architectural features of some of the early "RISC"
>processors - I still think that register windows are a poor design 
>choice in most cases.  It is surprising to me that they are so popular,
>.  I wish that the chip real estate devoted to register windows would
>be devoted to a smaller number (32 say) all purpose 64 bit registers
>with better floating point support.

	Hear, hear!

------------------------------------------------------------------------
Laurence G. Yaffe			lgy@pupthy.princeton.edu
Department of Physics			lgy@pucc.bitnet
Princeton University			...!princeton!pupthy!lgy
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