Path: utzoo!mnetor!uunet!seismo!sundc!pitstop!texsun!texsun.central.sun.com!convex!authorplaceholder
From: gruger@convex.UUCP
Newsgroups: comp.arch
Subject: Re: SPARC and multiprocessing
Message-ID: <63900014@convex>
Date: 3 May 88 22:58:00 GMT
References: <51321@sun.uucp>
Lines: 27
Nf-ID: #R:sun.uucp:-5132100:convex:63900014:000:1308
Nf-From: convex.UUCP!gruger    May  3 17:58:00 1988


>/* Written  5:51 pm  May  2, 1988 by jeff@alliant.Sun.Com
>	...  It is a much more
>	complicated procedure to "watch" these addresses.  With a virtual
>	cache, each physical address on the bus must first be translated to
>	it's corresponding virtual address through some sort of reverse TLB,
>	then the address can be provided to the bus watcher to see if the data
>	is in the cache.
>	...In order to
>	properly snoop, all of the aliases must be checked for in the cache.
>	Another problem, is simply the implementation of the reverse TLB -
>	what happens when the reverse TLB misses?  Which set of page tables
>	should the TLB walk?

Nah, it ain't that hard.  One can have a virtually mapped, physically tagged
cache.  As the virtual cache is filled with data, the translated physical
address from the MMU is written into the tag RAMs.  The physical tags are 
then used by the bus watcher to selectively invalidate the cache entries.

This is in fact how cache coherency is maintained in the Convex C-2 machines.
Each of the CPUs has a set of remote invalidation tag memories which watches
all of the other physical address buses (3 other CPUs and one I/O).  When 
there is a hit, the validity bits are cleared for that particular entry in 
the virtually mapped cache.  

Jeff Gruger
(ihnp4!convex!gruger)