Path: utzoo!yunexus!geac!daveb
From: daveb@geac.UUCP (David Collier-Brown)
Newsgroups: comp.arch
Subject: Re: SPARC and multiprocessing (large read latencies)
Keywords: prefetch, pipelines
Message-ID: <2710@geac.UUCP>
Date: 6 May 88 18:47:12 GMT
Article-I.D.: geac.2710
Posted: Fri May  6 14:47:12 1988
References: <1521@pt.cs.cmu.edu> <28200135@urbsdc> <4921@bloom-beacon.MIT.EDU> <51409@sun.uucp> <8029@pur-ee.UUCP> <381@mancol.UUCP>
Reply-To: daveb@geac.UUCP (David Collier-Brown)
Organization: The Geac Plumbing Department.
Lines: 17

In article <381@mancol.UUCP> jh@mancol.UUCP (John Hanley) writes:
>Something I haven't seen is the above PREFETCH instructions implemented in
>hardware.  Call it an intelligent look-ahead cache, or an aux. CPU. 
>Predictive memory requests are made not only on the instruction stream,
>but also on the data stream, a few instructions ahead of time.  

Well, not on a RISC machine...  It is logically similar to (perhaps
identical to?) a pipeline on a CISC.  My old 'bun used to look
"forward" in the instruction stream with wild abandon, beacuse it
took so long to decode the instructions (:-)).

--dave (data, now, is quite a different matter) c-b
-- 
 David Collier-Brown.                 {mnetor yunexus utgpu}!geac!daveb
 Geac Computers International Inc.,   |  Computer Science loses its
 350 Steelcase Road,Markham, Ontario, |  memory (if not its mind) 
 CANADA, L3R 1B3 (416) 475-0525 x3279 |  every 6 months.