Path: utzoo!yunexus!geac!daveb
From: daveb@geac.UUCP (David Collier-Brown)
Newsgroups: comp.arch
Subject: Re: Is the Intel memory model safe from NO-ONE ?!?
Summary: No.
Keywords: 386 intel memory protection management model segmented
Message-ID: <2711@geac.UUCP>
Date: 6 May 88 18:57:05 GMT
Article-I.D.: geac.2711
Posted: Fri May  6 14:57:05 1988
References: <1806@obiwan.mips.COM> <2904@omepd> <353@cf-cm.UUCP>
Reply-To: daveb@geac.UUCP (David Collier-Brown)
Organization: The Geac Multics Department.
Lines: 28

In article <353@cf-cm.UUCP> mch@computing-maths.cardiff.ac.uk (Major Kano) writes:
>   that made it so TECHNICALLY advanced [] ** WAS ** its memory management
>   and protection model. The 32-bit within-segment addresses are what
>   people have been waiting for for ages. I would question the fact that
>   only 16 bit selectors are avaliable, but I defy anyone to come up, in the
>   near or intermediate future, with an Intel-style memory model that is
>   better than Intel's, without opening up a whole can of voracious
>   memory-eating killer-worms at the descriptor table level.


  The problem with the 80xxx memory models is visibility: the basic
idea of a segment as a grouping mechanism is very old, and should
not be confused with the idea of a segment as a sort of "big page".

  If the segments are invisible to the HLL programmer (usually by
being "big enough"), they're a win.  The only thing is...
	16 bits of addressability is visibly too little
	32 bits has been described as too small
	36 bits was **FOUND** to be too small, about 10 years ago

  Programmer-visible segment limits are probably inadvisable, since
the only good sizes in computer science are zero, one and "as much as
you'd like".
-- 
 David Collier-Brown.                 {mnetor yunexus utgpu}!geac!daveb
 Geac Computers International Inc.,   |  Computer Science loses its
 350 Steelcase Road,Markham, Ontario, |  memory (if not its mind) 
 CANADA, L3R 1B3 (416) 475-0525 x3279 |  every 6 months.