Path: utzoo!attcan!uunet!seismo!sundc!pitstop!sun!amdahl!ames!lamaster
From: lamaster@ames.arc.nasa.gov (Hugh LaMaster)
Newsgroups: comp.arch
Subject: Re: Is the Intel memory model safe from NO-ONE ?!?
Message-ID: <8722@ames.arc.nasa.gov>
Date: 13 May 88 15:11:58 GMT
References: <353@cf-cm.UUCP> <3095@edm.UUCP> <20618@think.UUCP> <1988May12.162207.16764@utzoo.uucp>
Reply-To: lamaster@ames.arc.nasa.gov.UUCP (Hugh LaMaster)
Organization: NASA Ames Research Center, Moffett Field, Calif.
Lines: 27

In article <1988May12.162207.16764@utzoo.uucp> henry@utzoo.uucp (Henry Spencer) writes:
>Probably because practically every machine in existence routes *all*
>traps and interrupts to the kernel, which can pass them on to the user
>if it pleases.  I know of no machine, offhand, whose hardware has any
>notion of a "user handler".

Well, here's your first: the Cyber 205 architecture has a "data flag
branch register" which is under user control.  Part of the processor
context is this register which tells what to do with various
conditions as well as what conditions exist.
You can ignore conditions, trap to a user supplied error handler,
or trap to a default data flag branch manager subroutine, all in
the user's process address space, and without ever going to the kernel.
The price paid for this is the cost of one extra dedicated context
register and two regular registers (out of 256 on this machine).  It
should be noted that historically, CDC and Cray have provided a larger
set of user context registers (the "exchange package" or "invisible
package") which help provide fast context switches and reduce the cost
of handling interrupts.  At a cost of some expensive real estate -
high speed registers which are not available to the user.


-- 
  Hugh LaMaster, m/s 233-9,  UUCP {topaz,lll-crg,ucbvax}!
  NASA Ames Research Center                ames!lamaster
  Moffett Field, CA 94035    ARPA lamaster@ames.arpa
  Phone:  (415)694-6117      ARPA lamaster@ames.arc.nasa.gov