Path: utzoo!attcan!uunet!husc6!bloom-beacon!mit-eddie!ll-xn!ames!amdcad!light!bvs
From: bvs@light.uucp (Bakul Shah)
Newsgroups: comp.arch
Subject: User mode trap handlers (was: Is the Intel memory ...)
Message-ID: <1988May13.121424.9319@light.uucp>
Date: 13 May 88 19:14:22 GMT
References: <353@cf-cm.UUCP> <3095@edm.UUCP> <20618@think.UUCP> <1988May12.162207.16764@utzoo.uucp>
Reply-To: bvs@light.UUCP (Bakul Shah)
Organization: Light Systems, Mountain View, CA
Lines: 49

>> ... it traps into SUPERVISOR mode, even though the program
>> that executed the divide instruction was running in USER mode.  Why
>> should a zero-divide need to be handled by the protected kernel,
>> rather than simply trapping to a user handler?
>
>Probably because practically every machine in existence routes *all*
>traps and interrupts to the kernel, which can pass them on to the user
>if it pleases.  I know of no machine, offhand, whose hardware has any
>notion of a "user handler".

On a RISC processor the overhead to dispatch a user mode trap handler
can be sufficiently low to make their use practical.  This is certainly
true of the AMD 29000 processor.  Example:

supervisor_handler_N:
	mfsr    tpc, PC1          ; save the old PC in tpc
	mtsr    PC1, utrap        ; setup PC to return to user_handler_N
	add     tmp, utrap, 4     ;
	mtsr    PC0, tmp          ; need two PCs on this pipelined machine
	iret                      ; interrupt return

Here register utrap has the address of user_handler_N, PC1 and PC0 are
special registers that contain address of the instruction after the
trapped instruction and the next instruction after that.

Trap N is routed by hardware to supervisor_handler_N, which sets things
up so that interrupt return is to user_handler_N.

user_handler_N:
	...
	jmpi    tpc

The user mode handler does whatever is necessary and finally jumps to
the instruction after the trapped instruction.

This scheme takes 5 more instructions compared to a supervisor mode trap
handler for the same thing.  Actually, it turns out this is the *most*
efficient way of handling certain kinds of traps on the 29000.  When any
trap is taken, the virtual memory mapping is turned off (necessary since
traps don't nest on the 29k).  So if you want to use VM in a handler and
don't need access to any supervisor-only facility, you are better off
with user mode handlers than messing with various registers to do VM
operations on user's behalf.

----
Bakul Shah <..!{ucbvax,sun}!amdcad!light!bvs>

PS:  I have lied a little to get the main point across.  Interested
people can read the user's maunal for details on the 29k.