Path: utzoo!attcan!uunet!husc6!bloom-beacon!tut.cis.ohio-state.edu!rutgers!okstate!gregg
From: gregg@a.cs.okstate.edu (Gregg Wonderly)
Newsgroups: comp.arch
Subject: Re: Is the Intel memory model safe from NO-ONE ?!?
Message-ID: <3565@okstate.UUCP>
Date: 12 May 88 06:01:17 GMT
References: <353@cf-cm.UUCP>
Organization: Oklahoma State Univ., Stillwater
Lines: 44

Instruction stream references are vastly different from those of data, and
for that very reason, I would vote for a variable size segment capability.
To clarify, typically you either need a 'functional unit of a program' or
you don't i.e. you are only executing one procedure at a time, so either
the whole thing should be resident, or none of it (I don't write 4.2Gbyte
functions do you?).  Even for the 64K segment processors, the compiler
can discover how a local branch within a function > 64K should be
handled i.e. is it a NEAR or a FAR branch.

Data references on the other hand are highly erratic.  For this reason,
data memory management should be page oriented so that only the most
necessary portions are present.  Because of the typical way that data addresses
are calculated using integer arithmetic, the data address space should be
representable in a single general purpose register.  If variable length segments
are used, so that each data entity is contained within a segment, there
should be some paging mechanism provided within the segmentation to make
unreferenced address space available for allocation to other processes.

One of the major objections to the Intel segmentation is that when you finally
escape the space limitations by using Large/Huge models, you are carrying around
a lot more baggage in each instruction.  Random array references can not really
be done using integer arithmetic because some !@$#$$% engineer decided to place
the RPL bits and the LDT/GDT selector bit in the lower order bits of the
selector number.

OS/2 claims to support Huge model on the 80286, which sends shivers up my
spine.  Would someone care to tell me how one might arrive at a linear
address space (I could get real rich, fast)?  My speculation is that the
GDT is not used so therefore the 3 lower order bits are always set.  Thus,
normal integer arithmetic would cause these bits to be cleared when an
overflow from the offset portion carried into the selector portion.  Using
this selector would cause an addressing error.  The exception code could
then check those 3 bits, and re-set them to all ones, and restart the
instruction stream.  Presto, you have a linear address space.

THE PROGRAMMER SHOULD NEVER SEE A HARDWARE IMPOSED CONSTRAINT ON ADDRESS
SPACE REFERENCES.

Gregg Wonderly
Department of Computing and Information Sciences
Oklahoma State University

UUCP:      {cbosgd, ihnp4, rutgers}!okstate!gregg
Internet:  gregg@A.CS.OKSTATE.EDU