Path: utzoo!attcan!uunet!lll-winken!lll-tis!ames!ll-xn!mit-eddie!rutgers!aramis.rutgers.edu!constance.rutgers.edu!webber From: webber@constance.rutgers.edu (Bob Webber) Newsgroups: comp.arch Subject: Re: Do RISC Compilers Consider Multiprogramming? Keywords: RISC compiler context-switch architecture multiprogramming Message-ID: Date: 6 May 88 13:24:51 GMT References: <620@speedy.mcnc.org> Organization: Rutgers Univ., New Brunswick, N.J. Lines: 21 In article <620@speedy.mcnc.org>, davis@mcnc.org (Mark C. Davis) writes: > ... > Disclaimer: I believe that RISC is the best solution to low order > multiprogramming (like my workstation). But, there does seem to be this > application of uniprocessor high order multiprogramming that will not go > away (people wanting to put 40 users on a sun 4 and process control > with zillions of independent processes). The Mips R2000 (and presumably the R3000) has a large register set that can be organized as stack caches (perhaps even overlapping register sets?) or as separate process contexts. Clearly the designers wanted to make both options available to the software people. Whether actual systems based on them really do much with the feature in terms of making it available to the system users, however, I don't know. -------- BOB (webber@aramis.rutgers.edu ; rutgers!aramis.rutgers.edu!webber) p.s., in case it wasn't clear from context, the R2000/3000 are generally viewed as RISC chips although doubtless somewhere there is someone whose definition of RISC they don't fit -- the infinite variety of the universe is astounding, but why so much of that variety was concentrated in humanity is outright puzzling.