Path: utzoo!attcan!uunet!husc6!purdue!decwrl!amdcad!tim From: tim@amdcad.AMD.COM (Tim Olson) Newsgroups: comp.arch Subject: Re: Do RISC Compilers Consider Multiprogramming? Keywords: RISC compiler context-switch architecture multiprogramming Message-ID: <21653@amdcad.AMD.COM> Date: 17 May 88 15:57:48 GMT References: <620@speedy.mcnc.org> Reply-To: tim@amdcad.UUCP (Tim Olson) Organization: Advanced Micro Devices Lines: 21 In article webber@constance.rutgers.edu (Bob Webber) writes: | The Mips R2000 (and presumably the R3000) has a large register set that | can be organized as stack caches (perhaps even overlapping register | sets?) or as separate process contexts. Clearly the designers wanted | to make both options available to the software people. Whether actual | systems based on them really do much with the feature in terms of | making it available to the system users, however, I don't know. Uhhh.. I think you may have your processors confused, here. The Am29000 is the processor that has the large register file which can be used as a stack cache or as multiple banks (purely a software convention). All of our current software generates code for the stack-cache model, as that is the best in terms of performance, and matches most applications better (most real-time applications have more than the 8 tasks allowable simultaneously in the register file, so context-switch time, while on average very small, may sometimes be much larger.) -- Tim Olson Advanced Micro Devices (tim@amdcad.amd.com)