Path: utzoo!attcan!uunet!steinmetz!itsgw!nyser!cmx!billo
From: billo@cmx.npac.syr.edu (Bill O)
Newsgroups: comp.arch
Subject: Re: RISC != real-time control (actu
Message-ID: <494@cmx.npac.syr.edu>
Date: 18 May 88 02:28:29 GMT
References: <1924@sics.se>
Reply-To: billo@cmx.npac.syr.edu (Bill O'Farrell)
Distribution: comp
Organization: Northeast Parallel Architectures Center, Syracuse NY
Lines: 54

In article <1924@sics.se> aronsson@sics.se (Lars Aronsson) writes:

>Before I start: This might turn out to be Todays Dumb Suggestion.
>Maybe my ideas are already implemented on lots of systems or totally
>useless. Please, let me know!

Yes, I think they have been to a certain extent. More in a bit...

>
>As far as I know, RISC instruction caches are a gain only when the
>processor runs through loops. What about the ability to declare
>cache-resident functions (procedures/subroutines)? This might not be
>the solution to real-time applications, but seems potentially useful
>in many other cases.
>
>Things normally managed by super-CISC instructions (decimal
>arithmetics, string instructions and the like) in such machines, would
>then be done with neat library functions declared as "register". The
>CISC equivalent to this would be to allow users to define new machine
>instructions at run-time.
>
>Of course, you would have to decide on what to do on a context switch.
>Maybe the the register functions should belong to a shared library and
>be more or less permanently in the cache.

Actually, there is no need to use *associative* cache for this
purpose, because the "associative" part is really just a mechanism to
enable the computer to keep in fast memory a portion of the code which
it predicts will be referenced in the near future (the prediction is
usually based on past use). For functions declared as being "fast"
or, as suggested, "register", all you really need is good old
fashioned fast memory.

What follows are excerpts from a couple of recent (past few months)
postings relating to the way this sort of thing was done on the pdp 10
and 11 (the second excerpt gives new meaning to the declaration
"register")

[Dean W. Anneser, Pratt & Whitney Aircraft]
-We have 7 of these beasties [pdp-11/55], and they're still running
-strong.  The memory configuration is 0-32kw bipolar, and 32-124kw MOS.
-We keep the time- critical code in the bipolar.  DEC has never
-produced a faster PDP-11.  We have benchmarked and are currently using
-the 11/73, 11/83, and 11/84, and the 11/55 will still run circles
-around them...

[Brian Utterback, Cray Research Inc.]
-Another advantage the PDP-10 had by mapping the registers to the
-memory space, other than indexing, was in execution.  You could load a
-short loop into the registers and jump to them!  The loop would run
-much faster, executing out of the registers.

Bill O'Farrell, Northeast Parallel Architectures Center at Syracuse University
(billo@cmx.npac.syr.edu)