Path: utzoo!utgpu!water!watmath!clyde!att!pacbell!ames!necntc!encore!bartlett
From: bartlett@encore.UUCP (John Bartlett)
Newsgroups: comp.arch
Subject: Re: SPARC and multiprocessing (larg
Message-ID: <3091@encore.UUCP>
Date: 23 May 88 02:02:44 GMT
References: <2710@geac.UUCP> <63900015@convex>
Reply-To: bartlett@encore.UUCP (John Bartlett)
Organization: Encore Computer Corp, Marlboro, MA
Lines: 34

In article <63900015@convex> gruger@convex.UUCP writes:
>Which "two tag stores" are you referring to?   

In our system we have two separate tag stores, one for processor access
to the cache, one for bus invalidation.  This is because the bus and
the processors run on different clocks.

>By "fully associative"
>I take it you mean a true content addressable memory for the entire tag 
>memory??  I believe you only need to have high associativity when
>searching through multiple sets of your data cache.
>
>Our cache structures consist of:
>	a) a virtually addressed data RAM
>	b) a virtually addressed validity RAM 
>	c) a physically addressed tag RAM
>The tag ram is only written as read data returns to the cache.  The 
>tag ram is read only as remote processor writes occur, and if there
>is a hit, the validity bits are cleared.
>
You must have some trick for insuring complete mapping between your virtual
index and your physical index.  In order to insure complete mapping, one
of them has to be fully associateive (yes CAM) does it not?  If you limit 
the combinations in some way to prevent this problem, don't you take a hit
on hit rate ? (oh, sorry 'bout the bad pun)


John Bartlett		{ihnp4,decvax,allegra,linus}!encore!bartlett
Encore Computer Corp.
257 Ceder Hill Street
Marlboro, Mass.  01752
(617) 460-0500

Opinions are not necessarily those of Encore Computer Corp.