Path: utzoo!utgpu!water!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!mailrus!nrl-cmf!ames!amdahl!drivax!riddle
From: riddle@drivax.UUCP (Riddle)
Newsgroups: comp.os.cpm
Subject: Re: Ithaca Intersystems 256KDR S-100 memory
Message-ID: <3406@drivax.UUCP>
Date: 17 May 88 18:16:04 GMT
References: <1481*kenw@noah.arc.cdn> <898@pilchuck.Data-IO.COM>
Reply-To: riddle@drivax.UUCP (Riddle)
Organization: Digital Research Inc
Lines: 22

I liked <898@pilchuck.Data-IO.COM>'s solution to the S-100 24-bit addressing
to the old Z80-bank switching kludge.  Ithaca Intersystems took a simular
approch, the CPU board had a simple MMU which provided 8 banks of 16 4K
memory address translation.  That's how MP/M and banked CP/M plus were
implimented to look like a banked system, while DMA was still 24-bit addresses.

BUT........I have an easier (better :-)) fix for you people with Cromemco or
Advanced Micro type CPUs.

I will provide you schmatics of a one chip addition to the 256K board, so that
it will read the bank switch lines from the S-100 bus.

.........BONUS........make board into 1 meg.............BONUS............

It will also show how add address decoding for using 256K mem chips, giving
you 1 meg capacity on the board.

I can't/won't character draw it here, so Email me your Postal address and I
will USMail a copy to you.
					Riddle
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