Path: utzoo!attcan!uunet!mcvax!enea!chalmers!myab!lars
From: lars@myab.UUCP (Lars Pensj|)
Newsgroups: comp.sys.nsc.32k
Subject: Re: commentary on "532 Manifesto"
Keywords: 32532, PD board
Message-ID: <355@myab.UUCP>
Date: 18 May 88 09:55:49 GMT
References: <17145@gatech.edu>
Reply-To: lars@myab.UUCP (Lars Pensj|)
Organization: Myab Gothenburg, Sweden
Lines: 38

In article <17145@gatech.edu> ken@gatech.edu (Ken Seefried iii) writes:
>
>	Daryl McDaniel mentioned the fact that he has been designing '532
>systems with the AT&T 32104 DMA chip.  The more i look at the specs for the 
>32104, the better this sounds.  I vote for DMA.  I really think for a chip
>with the speed of the '532, we need it.
>

We have considered designing a 532-system with 32104 DMA. However, there are
problems with this chip:

1. It has another byte order than 532. That means that you have to swap
   the bytes in the system bus interface (nobody want tapes with swapped bytes).

   Now the software have to swap bytes in addresses. Ugly (and some overhead) !

2. The data sheets (WE 32104 DMA Controller Information Manual) says:
   "Memory-to-peripheral transfers should not use request chaining if there
   is multiple channel activity".
   My interpretation of this is that you can not use data chaining if you use
   more than one channel. This is intolerable, because data chaining is
   very important if you want fast I/O.

2. The data sheets (WE 32104 DMA Controller Information Manual) says:
   "The source address of memory-to-peripheral transfers must be word-aligned
   (i.e., addresses divisible by 4)."
   If you use SCSI with disconnect-reconnect, the dma have to be able to
   restart on any byte boundary.
   Also when you do a 'raw' transfer from user memory, the data can
   have any alignment.
   It is not acceptable that the driver have to check and fix these
   problems.


Now I wonder: are there really no DMA chip which do not have these problems ?
-- 
    Lars Pensj|
    {decvax,philabs}!mcvax!enea!chalmers!myab!lars