Path: utzoo!attcan!uunet!husc6!bloom-beacon!gatech!udel!princeton!phoenix!pupthy2!lgy
From: lgy@pupthy2.PRINCETON.EDU (Larry Yaffe)
Newsgroups: comp.arch
Subject: Re: integer multiplies (Was: architecture/implementation -- MIPS)
Message-ID: <3006@phoenix.Princeton.EDU>
Date: 24 May 88 15:44:35 GMT
References: <2231@gumby.mips.COM>
Sender: news@phoenix.Princeton.EDU
Reply-To: lgy@pupthy2.PRINCETON.EDU (Larry Yaffe)
Organization: Physics Dept, Princeton Univ
Lines: 41

In article <2231@gumby.mips.COM> earl@mips.COM (Earl Killian) writes:

    [[ Much information about the R/3000 including: ]]

>> Integer Multiply/Divide
>
>How is multiply is implemented [software, multiply step, hardware]? hardware
>How many cycles to perform 32x32->32 multiply? 13
						^^
>
>> Floating Point
>
>What are the floating point operation latency/issue/repeats?
>
>		 32-bit		 64-bit		 80-bit
>	mul	 4/ 1/ 4	 5/ 1/ 5	 n.a.
		^^
>UUCP: {ames,decwrl,prls,pyramid}!mips!earl
>USPS: MIPS Computer Systems, 930 Arques Ave, Sunnyvale CA, 94086

    I'm curious and a little surprised about the relative speed of
integer and floating point multiplies.  Are integer multiplies
substantially less frequent than floating point mults (in some
selection of "real" programs) that integer multiply being three
times slower than f.p. is not a significant bottleneck?
What fraction of integer multiplies are not multiplications
by small compile-time constants (in that same set of programs)?
Since MIPS Co. is reputed to have studied real programs when
considering design trade-off's, I'm hoping someone there can
offer some insight.

    Also, despite having looked through the MIPS architecture book
quite carefully, I can not find any mention of the latency of integer
multiply or divide operations.  Am I just getting sloppy, or is the
information really missing?

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Laurence G. Yaffe			Internet: lgy@pupthy.princeton.edu
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