Path: utzoo!utgpu!water!watmath!clyde!att!osu-cis!killer!ames!lll-tis!lll-winken!lll-crg.llnl.gov!brooks
From: brooks@lll-crg.llnl.gov (Eugene D. Brooks III)
Newsgroups: comp.arch
Subject: Re: architecture/implementation -- 88000
Message-ID: <7794@lll-winken.llnl.gov>
Date: 26 May 88 21:40:46 GMT
References: <2232@gumby.mips.COM> <798@nud.UUCP>
Sender: usenet@lll-winken.llnl.gov
Reply-To: brooks@lll-crg.llnl.gov.UUCP (Eugene D. Brooks III)
Organization: Lawrence Livermore National Laboratory
Lines: 3

In article <798@nud.UUCP> tom@nud.UUCP (Tom Armistead) writes:
>    Support for multiprocessing via cache coherency features of cache
Lets hear about these very IMPORTANT features in detail.  Anyone have
this information available to them?