Path: utzoo!attcan!uunet!husc6!uwvax!oddjob!ncar!noao!mcdsun!nud!df
From: df@nud.UUCP (Dale Farnsworth)
Newsgroups: comp.arch
Subject: Re: architecture/implementation -- 88000
Message-ID: <799@nud.UUCP>
Date: 25 May 88 23:04:41 GMT
References: <2232@gumby.mips.COM>
Reply-To: df@nud.UUCP (Dale Farnsworth)
Organization: Motorola Microcomputer Division, Tempe, Az.
Lines: 37

Earl Killian (earl@mips.COM) writes:
> (Thanks to Andrew Klossner for his help on this one.)

I am pleased that Earl and Andrew made this available to the net.

> > Architecture Reference
> Where is the architecture fully described?
> 
>   -- MC78000 User's Manual Revision 0.4, October 7, 1987, Advanced
>      Information (100+ page document, describes registers,
>      instructions, exception processing, and timing information in
>      detail; it has no doubt been renamed by now)

Also marked Motorola Confidential/Proprietary.  The most recent version
is MC88100 User's Manual Revision 0.6, April 6, 1988, Advanced
Information.

>   -- MC78200 User's Manual Revision 0.1, November 29, 1987, Advanced
>      Information (80+ page document, like above but includes
>      architecture changes which will appear in the production chip)

Current version: MC88200 User's Manual Revision 0.4 Preliminary Copy,
April 19, 1988, Advanced Information.

> The instruction and data pipelines are exposed to software.

This could be misunderstood.  The pipelines are only exposed to
the exception handler.  Hardware register scoreboarding is used
by the chip so compilers are *not required* to do pipeline
instruction scheduling.

Again, thanks for the excellent information.

-Dale

-- 
Dale Farnsworth		602-438-3092	uunet!unisoft!nud!df