Path: utzoo!attcan!uunet!husc6!bloom-beacon!mit-eddie!bbn!rochester!crowl
From: crowl@cs.rochester.edu (Lawrence Crowl)
Newsgroups: comp.arch
Subject: Stack Architectures Can Have Registers
Keywords: RISC, real-time
Message-ID: <10076@sol.ARPA>
Date: 26 May 88 19:27:46 GMT
Reply-To: crowl@cs.rochester.edu (Lawrence Crowl)
Organization: U of Rochester, CS Dept, Rochester, NY
Lines: 20

I have notices a pervasive, but unwarrented, assumption reguarding stack
architectures.  Namely, that the push and pop operations are to memory.  This
need not be the case.  The critical feature of a stack architecture is the
expression evaluation mechanism, not the lack of registers.  So, the key issue
is "0 operand" instructions versus "2 or 3 operand" instructions.  When
comparing a register-to-register architecture with a stack architecture, one
must allow the stack architecture to have registers.  

This quells two objections to stack architectures.  The first objection is that
stack architectures must go to memory for local variables while register-to-
register architectures need not.  A stack architecture with registers will have
the same fast storage.  The second objection is that common subexpressions are
more difficult.  This is only marginally true.  A simple "copy top of stack to
register" instruction will succeed in saving the results of the subexpression.
The identification of common subexpressions is architecture independent.

-- 
  Lawrence Crowl		716-275-9499	University of Rochester
		      crowl@cs.rochester.edu	Computer Science Department
...!{allegra,decvax,rutgers}!rochester!crowl	Rochester, New York,  14627