Path: utzoo!attcan!uunet!husc6!necntc!ima!think!barmar
From: barmar@think.COM (Barry Margolin)
Newsgroups: comp.arch
Subject: Re: Stack Architectures Can Have Registers
Keywords: RISC, real-time
Message-ID: <21242@think.UUCP>
Date: 26 May 88 22:56:51 GMT
References: <10076@sol.ARPA>
Sender: usenet@think.UUCP
Reply-To: barmar@kulla.think.com.UUCP (Barry Margolin)
Organization: Thinking Machines Corporation, Cambridge, MA
Lines: 22

In article <10076@sol.ARPA> crowl@cs.rochester.edu (Lawrence Crowl) writes:
>This quells two objections to stack architectures.  The first objection is that
>stack architectures must go to memory for local variables while register-to-
>register architectures need not.

The machine I use, a Symbolics 36xx, solves this problem without
adding user-visible registers.  Instead, the top N words of the stack
are stored in high-speed cache memory.  I don't know what N is, but I
think it is several hundred.  This provides the speed of registers
without complicating the rest of the architecture.  I think many
stack-based architectures use a similar scheme.

This is similar to the PDP-10's registers, which could also be
accessed as the first 16 words of memory.  In fact, since the PC could
point to these locations, it was possible to run a program in a PDP-10
with no memory installed!

Barry Margolin
Thinking Machines Corp.

barmar@think.com
uunet!think!barmar