Path: utzoo!attcan!uunet!seismo!sundc!pitstop!sun!quintus!ok
From: ok@quintus.UUCP (Richard A. O'Keefe)
Newsgroups: comp.arch
Subject: Re: Stack Architectures Can Have Registers
Keywords: RISC, real-time
Message-ID: <1028@cresswell.quintus.UUCP>
Date: 27 May 88 05:20:00 GMT
References: <10076@sol.ARPA>
Organization: Quintus Computer Systems, Mountain View, CA
Lines: 14

In article <10076@sol.ARPA>, crowl@cs.rochester.edu (Lawrence Crowl) writes:
> I have noticed a pervasive, but unwarrented, assumption reguarding stack
> architectures.  Namely, that the push and pop operations are to memory.  This
> need not be the case.  The critical feature of a stack architecture is the
> expression evaluation mechanism, not the lack of registers.  So, the key issue
> is "0 operand" instructions versus "2 or 3 operand" instructions.

An example of this is the 80387 (maybe the 8087 is too, I just don't
happen to have a manual for it).

Are the bandwidth considerations between a CPU and a coprocessor such as
the 80387 significantly different from code density considerations?
That is:  were the 0-operand instructions put in the 80*87 to reduce
coprocessor interface time or for some other reason?