Path: utzoo!utgpu!water!watmath!clyde!att!osu-cis!tut.cis.ohio-state.edu!mailrus!ames!pasteur!ucbvax!decwrl!sun!pitstop!texsun!texsun.central.sun.com!convex!authorplaceholder
From: gruger@convex.UUCP
Newsgroups: comp.arch
Subject: Re: SPARC and multiprocessing (larg
Message-ID: <63900016@convex>
Date: 25 May 88 14:12:00 GMT
References: <3091@encore.UUCP>
Lines: 20
Nf-ID: #R:encore.UUCP:-309100:convex:63900016:000:897
Nf-From: convex.UUCP!gruger    May 25 09:12:00 1988


>/* Written  9:02 pm  May 22, 1988 by bartlett@encore.Sun.COM 
>You must have some trick for insuring complete mapping between your virtual
>index and your physical index.  In order to insure complete mapping, one
>of them has to be fully associateive (yes CAM) does it not?  If you limit 
>the combinations in some way to prevent this problem, don't you take a hit
>on hit rate ? (oh, sorry 'bout the bad pun)
>
>
>John Bartlett		{ihnp4,decvax,allegra,linus}!encore!bartlett
>Encore Computer Corp.

Its not a very fancy trick.  Physical index = virtual index.  Yes, the
cache has to be smaller than you might like it to maximize hit rate.
However, when you work with 5nsec ECL RAMs its difficult (impossible
today) to find any larger than 4K bits.  The raw cycle time this permits
more than compensates for a small sacrifice of hit rate.

Jeff Gruger
Convex Computer Corp.  {ihnp4!convex!gruger}