Path: utzoo!attcan!uunet!lll-winken!lll-tis!ames!mailrus!husc6!bloom-beacon!mit-eddie!uw-beaver!tektronix!orca!tekecs!frip!andrew
From: andrew@frip.gwd.tek.com (Andrew Klossner)
Newsgroups: comp.arch
Subject: 88k cache details
Message-ID: <10025@tekecs.TEK.COM>
Date: 27 May 88 21:06:24 GMT
References: <2232@gumby.mips.COM> <798@nud.UUCP> <7794@lll-winken.llnl.gov>
Sender: andrew@tekecs.TEK.COM
Organization: Tektronix, Wilsonville, Oregon
Lines: 15

>>    Support for multiprocessing via cache coherency features of cache
> Lets hear about these very IMPORTANT features in detail.  Anyone have
> this information available to them?

I have the documentation, but I'm not a cache expert and if I try to
summarize this in a net article I'll probably botch it.  If you're
really interested, I refer you to the references mentioned in other
comp.arch articles; a call to a Motorola sales office should turn them
up.  (Or maybe not ... has anyone not in the 88open consortium tried
this?  Is this material actually available to the public now?)

The 88200 manual completely describes the cache coherency protocols,
including some pretty complicated state diagrams.

  -=- Andrew Klossner   (decvax!tektronix!tekecs!andrew)       [UUCP]
                        (andrew%tekecs.tek.com@relay.cs.net)   [ARPA]