Path: utzoo!attcan!uunet!lll-winken!lll-tis!helios.ee.lbl.gov!pasteur!ucbvax!decwrl!pyramid!prls!mips!mash From: mash@mips.COM (John Mashey) Newsgroups: comp.arch Subject: Re: Intel RISC <> 80960 : true or false ? and 80486 Keywords: 88000 risc intel motorola clipper c100 c300 Message-ID: <2268@winchester.mips.COM> Date: 28 May 88 17:24:06 GMT References: <411@cf-cm.UUCP> Reply-To: mash@winchester.UUCP (John Mashey) Organization: MIPS Computer Systems, Sunnyvale, CA Lines: 24 In article <411@cf-cm.UUCP> mch@computing-maths.cardiff.ac.uk (Major Kano) writes: ... > As for the 80486, S. McGready had this to say: >>You will hear claims that the 486 uses "RISC design techniques" to reduce >>the number of clocks per instruction. Do not misinterpret this as a statement >>that the *86 family is suddenly a RISC architecture. > I rather think most people will assume this to mean a 68030/C100 rip-off (:-) >that is, Harvard inside with RISC core, JVN outside, amongst other things. >(Rather what I'd sort-of hoped the '386 to be when I first knew about it, in >late 1985.) I'm not sure where the "rip-off" part comes from. Making CISC architectures go faster by making them more RISClike on the inside has a long tradition amongst mainframes and superminis. It is not surprising that similar techniques would be used with CISC micros as the necessary silicon becomes available. Given everything else a 386 needs to do, it doesn't seem like there was enough silicon in that technology round to do the other things that were hoped-for. -- -john mashey DISCLAIMER: UUCP: {ames,decwrl,prls,pyramid}!mips!mash OR mash@mips.com DDD: 408-991-0253 or 408-720-1700, x253 USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086