Path: utzoo!attcan!uunet!mcvax!ukc!reading!onion!cf-cm!mch
From: mch@computing-maths.cardiff.ac.uk (Major Kano)
Newsgroups: comp.arch
Subject: Cretinous status/control register access (Was: Re: 80960 IO)
Summary: If I wanted a write-only register, I'd cover the bus in diodes -|>|- !
Keywords: status registers control registers IO chips uarts usarts disk serial
Message-ID: <418@cf-cm.UUCP>
Date: 27 May 88 11:45:19 GMT
References: <3358@omepd> <10320@steinmetz.ge.com> <40@radix> <11026@mimsy.UUCP> <253@babbage.acc.virginia.edu> <1086@mcgill-vision.UUCP>
Reply-To: mch@computing-maths.cardiff.ac.uk (Major Kano)
Organization: University College Cardiff, Wales, United Kingdom
Path: utzoo!attcan!uunet!mcvax!ukc!reading!onion!cf-cm!mch
From: mch@computing-maths.cardiff.ac.uk (Major Kano)
Newsgroups: comp.arch
Subject: Cretinous status/control register access (Was: Re: 80960 IO)
Summary: If I wanted a write-only register, I'd cover the bus in diodes -|>|- !
Keywords: status registers control registers IO chips uarts usarts disk serial
Message-ID: <418@cf-cm.UUCP>
Date: 27 May 88 11:45:19 GMT
References: <3358@omepd> <10320@steinmetz.ge.com> <40@radix> <11026@mimsy.UUCP> <253@babbage.acc.virginia.edu> <1086@mcgill-vision.UUCP>
Reply-To: mch@computing-maths.cardiff.ac.uk (Major Kano)
Lines: 50


   Hi there y'all. Don't ya' jes get sick an' tired of write-only control
registers and the like. (Hit 'n' if you couldn't give a 6554 status reg !)

In article <1086@mcgill-vision.UUCP> mouse@mcgill-vision.UUCP (der Mouse) writes:
>In article <253@babbage.acc.virginia.edu>, mac3n@babbage.acc.virginia.edu (Alex Colvin) writes:
>>> Caching is not the only problem with I/O devices.  It is (was?)
>>> common practice for status registers to be cleared upon being read.
>> All too common a practice!  Stop it!  If I'd 'a wanted it cleared I'd
>> 'a done a read-and-clear!
>
>How many machines *have* a read-and-clear instruction?  (No, the
>read-and-clear must be atomic, you're not allowed to use two
>instructions to do it.)

Why not have writeable status registers (a la 80X87) ?
Now try it like this:

load cpu_reg, io_device.status_word          ; clears status flags in io_device

store cpu_reg, where_you_wanted_status_held  ; put reg contents where you were
                                             ; going to use them in the program

or  cpu_reg, set_mask         }              ; code to operate on reg to
and cpu_reg, not clear_mask   } or whatever  ; selectively clear or set various
xor cpu_reg, not_mask         }              ; io_device status flag bits.

store cpu_reg, io_device_status_word         ; reload io_device.status_register

   This stops (if you want) further exceptions and leaves alone those flags
you want left alone.

(Intel 80X87: We don't need it anyway -- we have a NO-WAIT form ! NYAAHH !
 (several ":-)"'s ))

   A related idiosyncracy is write-only control registers, which on various
brain-damaged chips, share the (R/O) status reg addresses. Look at the BBC micro
which has to keep OS copies of every control register write to the (I think)
6554.

   Can anyone out there who designs these things or knows more than I do (not
difficult :-) say why these abominations exist or if (shock horror !) there is
actually a good reason for it ?

Thanks and regards,
-- 
Martin C. Howe, University College Cardiff | "C", adj; means  | I'm Motorhead; 
mch@vax1.computing-maths.cardiff.ac.uk.    | "write-only".    | Remember me now,
-------------------------------------------+------------------+ Motorhead;     
These opinions are mine, but YOU can have them for a few $$ ! | ALL RIGHT !