Path: utzoo!attcan!uunet!mcvax!ukc!reading!onion!cf-cm!mch
From: mch@computing-maths.cardiff.ac.uk (Major Kano)
Newsgroups: comp.arch
Subject: Re: RISC vs CISC on Low-End Processors
Summary: Request for information
Keywords: RISC, real-time
Message-ID: <419@cf-cm.UUCP>
Date: 27 May 88 11:51:10 GMT
References: <1521@pt.cs.cmu.edu> <1532@pt.cs.cmu.edu> <476@pcrat.UUCP> <833@imagine.PAWL.RPI.EDU> <3444@omepd> <492@pcrat.UUCP> <9561@sol.ARPA>
Reply-To: mch@computing-maths.cardiff.ac.uk (Major Kano)
Organization: University College Cardiff, Wales, United Kingdom
Lines: 25

In article <9561@sol.ARPA> crowl@cs.rochester.edu (Lawrence Crowl) writes:

(* stuff deleted *)

>These points taken together seem to indicate that we want neither RISC nor
>CISC, but the appropriate compromise.  The CRISP processor appears to have
>addressed this compromise well.  I do not know enough about the architecture
>to say whether or not it meets the requirements, but it appears much closer
>than many other architectures.   
>-- 
>  Lawrence Crowl		716-275-9499	University of Rochester
>		      crowl@cs.rochester.edu	Computer Science Department
>...!{allegra,decvax,rutgers}!rochester!crowl	Rochester, New York,  14627

   Sounds ok at first. Would anyone who can please remind me just what the CRISP
architecture is. I HAVE heard about it, but long ago. E-mail please, no need to
clutter up the net. If enough I'll summarise.

Thanks very much in advance;
regards,
-- 
Martin C. Howe, University College Cardiff | "C", adj; means  | I'm Motorhead; 
mch@vax1.computing-maths.cardiff.ac.uk.    | "write-only".    | Remember me now,
-------------------------------------------+------------------+ Motorhead;     
These opinions are mine, but YOU can have them for a few $$ ! | ALL RIGHT !