Path: utzoo!attcan!uunet!husc6!bloom-beacon!mit-eddie!uw-beaver!tektronix!reed!kamath From: kamath@reed.UUCP (Sean Kamath) Newsgroups: comp.sys.apple Subject: Re: Rocket and Zip Chips Message-ID: <9418@reed.UUCP> Date: 26 May 88 01:58:35 GMT References: <67.011023@adam.DG.COM> Reply-To: kamath@reed.UUCP (Sean Kamath) Organization: Reed College, Portland OR Lines: 30 In article <67.011023@adam.DG.COM> Bruce_Kahn%MAYTAG.CEO.DG.COM@adam.dg.com writes: > > Why is it that these speed chips for the Apple // say they can >speed up EXTERNAL devices when their clocks that are faster are >internal to them selves. I never realized that the 6502 had its own >clock output as well ;^). Can someone tell me (and the rest of the >world) how this amazing thing may be accomplished? Osmosis?!? Yes, the 6502 has two clock, but they are internal, and have nothing to do with the world. Similarly, the ZIP/Rocket chip have their own internal clocks. However, that clock is changable. What makes them fast is disk caching. This is the reason the Rocket chip says they are compatible with DMA devices, but only at 1 MHz. Simply put, the chip has a gob 'o memory onboard (a gob is defined as "enough") which it reads in from RAM/ROM at normal speed. By normal speed, I mean as fast as the circuitry allows. Once it is in the cache memory, it can by "used" by the CPU at it's own pace. Unfortunately, if a DMA device comes in and modifies the "real" memory when it's in the cache, things may or may not die a horrible death. If anyone wants a little longer dissertation on the concept, send me e-mail. Sean Kamath -- UUCP: {decvax allegra ucbcad ucbvax hplabs ihnp4}!tektronix!reed!kamath CSNET: reed!kamath@Tektronix.CSNET || BITNET: reed!kamath@PSUVAX1.BITNET ARPA: reed!kamath@PSUVAX1.CS.PSU.EDU US Snail: 3934 SE Boise, Portland, OR 97202-3126 (I hate 4 line .sigs!)