Path: utzoo!dciem!nrcaer!scs!spl1!laidbak!att!pacbell!ames!ncar!noao!mcdsun!nud!tom
From: tom@nud.UUCP (Tom Armistead)
Newsgroups: comp.arch
Subject: Re: architecture/implementation -- 88000
Message-ID: <803@nud.UUCP>
Date: 1 Jun 88 20:17:54 GMT
Article-I.D.: nud.803
References: <2232@gumby.mips.COM> <798@nud.UUCP> <7794@lll-winken.llnl.gov>
Reply-To: tom@nud.UUCP (Tom Armistead)
Organization: Motorola Microcomputer Division, Tempe, Az.
Lines: 26

>>    Support for multiprocessing via cache coherency features of cache
>Lets hear about these very IMPORTANT features in detail.  Anyone have
>this information available to them?

In brief:

    The 88200 chip contains logic that allows it to monitor the activities
of other 88200s in the system (including other processor's 88200s).  If 
an 88200 attempts to access a location in memory which does not contain
valid data (i.e. its "real" contents are in cache), then the 88200 containing
the correct data will preempt the access and update main memory.  The first
88200 will then continue the access and get the correct data.  This is referred
to as "snooping" and is performed by the 88200 chips themselves - software is
required to take no action (other than configuring the 88200's in snoop mode)
to maintain cache coherency between multiprocessors.  "Snooping" takes a 
large burden off of the work required to implement a multiprocessing system.

     Of course semaphoring is supported as well.

     I could post lots more but at this time have to limit my comments to
that information which has been released to the public.  The above is 
also discussed in the Technical summary of the MC88200.  
-- 
Just a few more bits in the stream.

The Sneek