Path: utzoo!attcan!uunet!husc6!think!ames!elroy!cit-vax!mangler
From: mangler@cit-vax.Caltech.Edu (Don Speck)
Newsgroups: comp.arch
Subject: Maximum MIPS for a given memory bandwidth?
Message-ID: <6921@cit-vax.Caltech.Edu>
Date: 13 Jun 88 02:46:04 GMT
Distribution: na
Organization: California Institute of Technology
Lines: 33

A while ago, Rick Richardson was looking for a microprocessor
that could squeeze 4000 Dhrystones out of a 4 MHz 16-bit bus.

Is this even possible?	That's only 3 MB/s of bandwidth per MIPS,
barely enough to fetch instructions.  Even the MC68010, which was
designed for slow memory, needs more like 7 MB/s per MIPS.

What's the lowest memory/cache bandwidth requirement per MIPS that
has been attained?  I.e. please add some numbers to this table:

  Processor	    avg read	bus	bandwidth	 MB/s:MIPS
		     latency   width   at the CPU   MIPS   ratio
SUN2 (68010)	      400ns	 16	  5 MB/s     0.7     7
Microvax II	      400ns	 32	 10 MB/s     0.9    11
VAX-11/750	     ~440ns	 32	  9 MB/s     0.6    15
VAX-11/780	     ~440ns	 32	 12 MB/s     1.0    12
PDP-11/55	      300ns	 16	  7 MB/s      1?     7?
88000		       45ns?	 32	185 MB/s?    17     11?
Cray-1S 	      137ns	 64	640 MB/s     20?    32?
16 MHz MIPSco	       ?	 32	120 MB/s?    10     13?
70 MHz WM	       ?	 32    3000 MB/s?   100?    30?
Acorn RISC Machine		 32			     ?

(I'm less sure about numbers appearing later in the table).

I'm wondering if there is some formula for the maximum number of
MIPS that can be extracted from a memory system, based on its
bandwidth, bus size, and latency, i.e. "with that memory/cache
system you can't get more than N mips"?  With a large enough table
of the above type, perhaps one could derive some rules of thumb in
this direction?

Don Speck   speck@vlsi.caltech.edu  {amdahl,ames!elroy}!cit-vax!speck