Path: utzoo!attcan!uunet!cbmvax!jesup
From: jesup@cbmvax.UUCP (Randell Jesup)
Newsgroups: comp.arch
Subject: Re: Maximum MIPS for a given memory bandwidth?
Message-ID: <4009@cbmvax.UUCP>
Date: 13 Jun 88 12:28:58 GMT
References: <6921@cit-vax.Caltech.Edu>
Reply-To: jesup@cbmvax.UUCP (Randell Jesup)
Distribution: na
Organization: Commodore Technology, West Chester, PA
Lines: 23

In article <6921@cit-vax.Caltech.Edu> mangler@cit-vax.Caltech.Edu (Don Speck) writes:
>  Processor	    avg read	bus	bandwidth	 MB/s:MIPS
>		     latency   width   at the CPU   MIPS   ratio
>SUN2 (68010)	      400ns	 16	  5 MB/s     0.7     7
>Microvax II	      400ns	 32	 10 MB/s     0.9    11
>VAX-11/750	     ~440ns	 32	  9 MB/s     0.6    15
>VAX-11/780	     ~440ns	 32	 12 MB/s     1.0    12
>PDP-11/55	      300ns	 16	  7 MB/s      1?     7?
>88000		       45ns?	 32	185 MB/s?    17     11?
>Cray-1S 	      137ns	 64	640 MB/s     20?    32?
>70 MHz WM	       ?	 32    3000 MB/s?   100?    30?
>16 MHz MIPSco	       ?	 32	120 MB/s?    10     13?
Try these (john?)               32+32	128?	     12?   ~10?

40 Mhz Rpm-40	      100ns	32+16   120 MB/s     33     ~4
			       data inst	   native

	If one is talking Vax Mips (which from the original msg we aren't):

40 Mhz Rpm-40	      100ns	32+16   120 MB/s    14-16  ~8-9
			       data inst	     vax

Randell Jesup, Commodore Engineering {uunet|rutgers|allegra}!cbmvax!jesup