Path: utzoo!attcan!uunet!husc6!bbn!gatech!amdcad!tim
From: tim@amdcad.AMD.COM (Tim Olson)
Newsgroups: comp.arch
Subject: Re: Maximum MIPS for a given memory bandwidth?
Message-ID: <22050@amdcad.AMD.COM>
Date: 13 Jun 88 18:22:21 GMT
References: <6921@cit-vax.Caltech.Edu>
Distribution: na
Organization: Advanced Micro Devices, Inc., Sunnyvale, Ca.
Lines: 81

In article <6921@cit-vax.Caltech.Edu>, mangler@cit-vax.Caltech.Edu (Don Speck) writes:
From To:mangler@cit-vax.Caltech.Edu Mon Jun 13 11:17:41 1988
Date: Mon, 13 Jun 88 11:17:42 PDT
To: mangler@cit-vax.Caltech.Edu  (Don Speck)
Subject: Re: Maximum MIPS for a given memory bandwidth?
In-Reply-To: Message from "Don Speck" of Jun 13, 88 at 2:46 am

| A while ago, Rick Richardson was looking for a microprocessor
| that could squeeze 4000 Dhrystones out of a 4 MHz 16-bit bus.
| 
| Is this even possible?	That's only 3 MB/s of bandwidth per MIPS,
| barely enough to fetch instructions.  Even the MC68010, which was
| designed for slow memory, needs more like 7 MB/s per MIPS.

The Am29000 gets 35600 Dhrystones (1.1) at 25MHz with two-cycle first
access, single-cycle burst caches.  This is well over the 1000
Dhrystones / MHz that Rick requested (although with a 32-bit bus instead
of 16 bits).  At 4 MHz, memory access times would be 250ns, easily
within DRAM range. 


| What's the lowest memory/cache bandwidth requirement per MIPS that
| has been attained?  I.e. please add some numbers to this table:
| 
|   Processor	    avg read	bus	bandwidth	 MB/s:MIPS
| 		     latency   width   at the CPU   MIPS   ratio
| SUN2 (68010)	      400ns	 16	  5 MB/s     0.7     7
| Microvax II	      400ns	 32	 10 MB/s     0.9    11
| VAX-11/750	     ~440ns	 32	  9 MB/s     0.6    15
| VAX-11/780	     ~440ns	 32	 12 MB/s     1.0    12
| PDP-11/55	      300ns	 16	  7 MB/s      1?     7?
| 88000		       45ns?	 32	185 MB/s?    17     11?
| Cray-1S 	      137ns	 64	640 MB/s     20?    32?
| 16 MHz MIPSco	       ?	 32	120 MB/s?    10     13?
| 70 MHz WM	       ?	 32    3000 MB/s?   100?    30?
| Acorn RISC Machine		 32			     ?

These numbers were derived from the Am29000 Architectural Simulator
running Dhrystone 1.1 (since the original question was pertaining to
Dhrystones).  The bandwidth requirements are actual, not theoretical
peak.  Since you didn't specify whether MIPS were native or VAX-MIPS, I
have calculated both:


			Am29000 (Video DRAM)
			--------------------
Ave Read Latency	160 ns (load/store/jump)
			 40 ns (instruction burst)

Bus Width		32 bits (* 2 -- separate instruction & data buses)


Bandwidth at CPU	44.7 MB/s instruction,
			11.5 MB/s data.

MIPS			12.7 Native, 15.2 VAX MIPS

MB/s/MIPS ratio:	3.70 (VAX)
			4.43 (Native)


			Am29000 (Caches)
			----------------
Ave Read Latency	 80 ns (load/store/jump)
			 40 ns (instruction burst)

Bus Width		32 bits (* 2 -- separate instruction & data buses)


Bandwidth at CPU	62.2 MB/s instruction,
			15.8 MB/s data.

MIPS			17.4 Native, 22.3 VAX MIPS

MB/s/MIPS ratio:	3.50 (VAX)
			4.48 (Native)


	-- Tim Olson
	Advanced Micro Devices
	(tim@delirun.amd.com)