Path: utzoo!attcan!uunet!zorch!vsi1!daver!
From: daver@daver.UUCP (Dave Rand)
Newsgroups: comp.arch
Subject: Re: Maximum MIPS for a given memory bandwidth?
Message-ID: <491@daver.UUCP>
Date: 13 Jun 88 23:18:28 GMT
References: <6921@cit-vax.Caltech.Edu> <22050@amdcad.AMD.COM>
Reply-To: daver@daver.UUCP (Dave Rand)
Distribution: na
Organization: Assn. for the prevention of Polar Bears and Kangaroos
Lines: 23

In article <22050@amdcad.AMD.COM> tim@amdcad.AMD.COM (Tim Olson) writes:
>
>			Am29000 (Video DRAM)
>MIPS			12.7 Native, 15.2 VAX MIPS
>			Am29000 (Caches)
>MIPS			17.4 Native, 22.3 VAX MIPS

I am confused. How can a risc machine have a higher "vax mips" than
native mips? MORE (not less) risc instructions are required to
do the same task, when compared to a vax.

If you are saying that the 29000 is 22.3 TIMES FASTER than a vax, then
say that - what you have said is not reasonable. I cannot believe that
you can execute a vax instruction in 78% of the time of a native
instruction (17.4/22.3).

This implies that, if you can execute a native instruction in 1 clock, that
you can execute a vax instruction (memory-to-memory add, for example), in
0.78 clocks!

-- 
Dave Rand
{pyramid|hoptoad|nsc|vsi1}!daver!daver