Path: utzoo!attcan!uunet!lll-winken!lll-tis!ames!ubvax!vsi1!daver!wombat!george
From: george@wombat.UUCP (George Scolaro)
Newsgroups: comp.arch
Subject: Re: Maximum MIPS for a given memory bandwidth?
Message-ID: <291@wombat.UUCP>
Date: 14 Jun 88 01:46:01 GMT
References: <6921@cit-vax.Caltech.Edu> <22050@amdcad.AMD.COM>
Reply-To: george@wombat.UUCP (George Scolaro)
Distribution: na
Organization: Assn. for the prevention of Polar Bears and Kangaroos
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In article <22050@amdcad.AMD.COM> tim@amdcad.AMD.COM (Tim Olson) writes:
>			Am29000 (Video DRAM)
>Bandwidth at CPU	44.7 MB/s instruction,
>			11.5 MB/s data.
>MIPS			12.7 Native, 15.2 VAX MIPS

>			Am29000 (Caches)
>Bandwidth at CPU	62.2 MB/s instruction,
>			15.8 MB/s data.
>
>MIPS			17.4 Native, 22.3 VAX MIPS

The implication is that the 29000 only requires the above bandwidth to
achieve the MIPS indicated.
The 29000 has a 100 Mbyte/second bus bandwidth. I am sure if you limited the
bus bandwidth to the above stated figures the MIPS would decrease quite a
bit. Sure, the average bandwidth required is as stated, but to achieve the
high MIPS you still need the peak 100 Mbytes/second, otherwise wait states
wouldn't hurt the 29000 performance, right?

-- george scolaro.
{pyramid|hoptoad|nsc|vsi1}!daver!wombat!george