Path: utzoo!attcan!uunet!husc6!uwvax!vanvleck!uwmcsd1!leah!itsgw!steinmetz!sungoddess!oconnor
From: oconnor@sungoddess.steinmetz (Dennis M. O'Connor)
Newsgroups: comp.arch
Subject: Re: Maximum MIPS for a given memory bandwidth?
Message-ID: <11234@steinmetz.ge.com>
Date: 14 Jun 88 13:23:02 GMT
References: <6921@cit-vax.Caltech.Edu>
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An article by jesup@cbmvax.UUCP (Randell Jesup) says:
] In article <...>mangler@cit-vax.Caltech.Edu (Don Speck) writes:
] >  Processor	    avg read	bus	bandwidth	 MB/s:MIPS
] >		     latency   width   at the CPU   MIPS   ratio
] 40 Mhz Rpm-40	      100ns	32+16   120 MB/s     33     ~4
] 			       data inst	   native
] 
] 	If one is talking Vax Mips (which from the original msg we aren't):
] 40 Mhz Rpm-40	      100ns	32+16   120 MB/s    14-16  ~8-9
] 			       data inst	     vax
] 
] Randell Jesup, Commodore Engineering {uunet|rutgers|allegra}!cbmvax!jesup

How soon they forget :-). Correct figures for bandwidth of the RPM40
are 160 MBytes/sec of data, and 80 MBytes/sec of instructions, for
a total of 240 MB/s of AVAILABLE bandwidth. Unless Randell is
quoting AVERAGE figures, but those would depend on the instruction
mix (i.e. the application).

Hi Randell : got your mail, mail to you bounced. I'll try again.
--
 Dennis O'Connor   oconnor%sungod@steinmetz.UUCP  ARPA: OCONNORDM@ge-crd.arpa
    "Never confuse USENET with something that matters, like PIZZA."