Path: utzoo!attcan!uunet!husc6!mailrus!ames!amdcad!tim
From: tim@amdcad.AMD.COM (Tim Olson)
Newsgroups: comp.arch
Subject: Re: Maximum MIPS for a given memory bandwidth?
Message-ID: <22063@amdcad.AMD.COM>
Date: 14 Jun 88 16:14:31 GMT
References: <6921@cit-vax.Caltech.Edu> <22050@amdcad.AMD.COM> <291@wombat.UUCP>
Reply-To: tim@amdcad.UUCP (Tim Olson)
Distribution: na
Organization: Advanced Micro Devices
Lines: 20

In article <291@wombat.UUCP> george@wombat.UUCP (George Scolaro) writes:
| The implication is that the 29000 only requires the above bandwidth to
| achieve the MIPS indicated.

Sorry -- I didn't mean to imply that.  Obviously if you want to execute
at close to an instruction per cycle, you must be able to supply that
peak rate at the pins.  However, I think that average bandwidth
requirements are much more interesting -- it tells more about the cost
and complexity of a memory design than the peak rating, and seemed to be
more in line with what the original poster was asking.

| The 29000 has a 100 Mbyte/second bus bandwidth.

Actually, it is 100MB/s for instruction and 100MB/s for data, although
the "sustained" peak is more like 170MB/s (running a series of loads or
stores). 

	-- Tim Olson
	Advanced Micro Devices
	(tim@delirun.amd.com)