Path: utzoo!attcan!uunet!husc6!mailrus!ames!ubvax!vsi1!daver!wombat!george
From: george@wombat.UUCP (George Scolaro)
Newsgroups: comp.arch
Subject: Re: Maximum MIPS for a given memory bandwidth?
Message-ID: <292@wombat.UUCP>
Date: 15 Jun 88 04:10:47 GMT
References: <6921@cit-vax.Caltech.Edu> <22050@amdcad.AMD.COM> <291@wombat.UUCP> <22063@amdcad.AMD.COM>
Reply-To: george@wombat.UUCP (George Scolaro)
Distribution: na
Organization: Assn. for the prevention of Polar Bears and Kangaroos
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In article <22063@amdcad.AMD.COM> tim@amdcad.UUCP (Tim Olson) writes:
>In article <291@wombat.UUCP> george@wombat.UUCP (George Scolaro) writes:
>| The implication is that the 29000 only requires the above bandwidth to
>| achieve the MIPS indicated.
>
>Sorry -- I didn't mean to imply that.  Obviously if you want to execute
>at close to an instruction per cycle, you must be able to supply that
>peak rate at the pins.  However, I think that average bandwidth
>requirements are much more interesting -- it tells more about the cost
>and complexity of a memory design than the peak rating,

Does average bandwith tell more about the memory design? Output from
the AMD29000 simulator (V4.21 PC) indicates that with 0 wait states
the device attains 20.71 MIPS. With 1 wait state on every memory access
the device attains 14.08 MIPS (Quote from Byte May 88). So, just 1 wait
state impacts the performance quite dramatically. For the 29000 to achieve
maximum performance the memory must support burst mode and as near to
zero wait states as possible. Thus even though the average bandwidth
requirement that was quoted was around 70 Mbytes/second, one wait state,
which reduces the bandwidth to 100 Mbytes/second has a major impact on
the Dhrystone benchmark. Of course adding cache changes the memory speed
requirements, but then cache is just high speed memory hidden behind a
high-tech. name.

>Actually, it is 100MB/s for instruction and 100MB/s for data, although
>the "sustained" peak is more like 170MB/s (running a series of loads or
>stores). 

Yeah, neat. I like the support for burst mode on both the instruction
and data paths. Also noted is support for burst write on the data path.

george scolaro.
{pyramid|hoptoad|nsc|vsi1}!daver!wombat!george