Path: utzoo!attcan!uunet!husc6!mailrus!iuvax!pur-ee!uiucdcs!uxc.cso.uiuc.edu!urbsdc!aglew
From: aglew@urbsdc.Urbana.Gould.COM
Newsgroups: comp.arch
Subject: Re: Maximum MIPS for a given memory ban
Message-ID: <28200161@urbsdc>
Date: 14 Jun 88 14:42:00 GMT
References: <6921@cit-vax.Caltech.Edu>
Lines: 14
Nf-ID: #R:cit-vax.Caltech.Edu:6921:urbsdc:28200161:000:383
Nf-From: urbsdc.Urbana.Gould.COM!aglew    Jun 14 09:42:00 1988


>I am confused. How can a risc machine have a higher "vax mips" than
>native mips? MORE (not less) risc instructions are required to
>do the same task, when compared to a vax.

Not always. Consider A=B+C, all in registers:
    VAX:
	mov rB,rA
	add rC,rA
    3 address RISC:
	add rA,rB,rC

So, we have an existence proof. What characteristics of the machine
actually let this happen?