Path: utzoo!attcan!uunet!lll-winken!lll-tis!mordor!joyce!ames!mailrus!iuvax!pur-ee!hankd
From: hankd@pur-ee.UUCP (Hank Dietz)
Newsgroups: comp.arch
Subject: Re: Maximum MIPS for a given memory bandwidth?
Summary: Getting even more blurry...
Message-ID: <8330@pur-ee.UUCP>
Date: 15 Jun 88 18:20:12 GMT
References: <6921@cit-vax.Caltech.Edu> <22050@amdcad.AMD.COM> <291@wombat.UUCP> <6955@cit-vax.Caltech.Edu>
Distribution: na
Organization: Purdue University Engineering Computer Network
Lines: 46

In article <6955@cit-vax.Caltech.Edu>, mangler@cit-vax.Caltech.Edu (Don Speck) writes:
...
> I consider caches to be part of the memory system, i.e. part of the
> von Neumann bottleneck.
...
> Instead of using the ambiguous term "MIPS", I should have said "number
> of times the speed of a VAX/780".  Unfortunately it wouldn't fit in the
> column headings.  Dhrystones would have been less ambiguous.  I didn't
> expect enough accuracy that it would make much difference.
...
> I still suspect that there's some lower bound on the number of
> bytes exchanged with cache/memory to perform the work of a
> "mythical" instruction.

What the *!%# are you measuring?

1. What are "MIPS"?
   (a) Is it millions of instructions executed per second or is it
       relative speed (VAX 780 = 1 MIP)?
   (b) Is it a peak rating or an average for some code?
   (c) If for a code, what code, with what precision requirements (e.g.,
       is it fair to compare 16-bit to 32-bit operations?), and is it the
       hand-generated best code or are we benchmarking compilers?

2. Bandwidth of what?
   (a) Do you measure bandwidth at:  Main memory?  Main memory with some
       VM paging overhead?  Caches?  On-chip (i.e., CPU internal) caches
       and registers?
   (b) Peak or average?
   (c) Any concept of shared access?  I.e., are you considering that I/O
       or other processors (e.g., an FPU) might share access to "memory"?
       If so, does their bandwidth count?

I gave you the (rather trivial) formula for determining the ratio in my last
posting...  let me just repeat that the minimum bandwidth is essentially
ZERO.  This would be achieved by a machine which had a single (probably
microcoded) instruction to, for example, perform the Dhrystone benchmark
using values kept in registers.  With no memory references (we don't count
program loading, right?), the number of MIPS has nothing to do with the
bandwidth.

SO, what is MY point?  The only way to get numbers to compare is to get
numbers relating comparable things...  ALL numbers should be as completely
broken-down as possible (e.g., list register, cache, main mem. bandwidth
separately) and fully labelled.

						-hankd