Path: utzoo!attcan!uunet!cbmvax!jesup
From: jesup@cbmvax.UUCP (Randell Jesup)
Newsgroups: comp.arch
Subject: Re: Maximum MIPS for a given memory bandwidth?
Message-ID: <4028@cbmvax.UUCP>
Date: 15 Jun 88 19:18:02 GMT
References: <6921@cit-vax.Caltech.Edu> <11234@steinmetz.ge.com>
Reply-To: jesup@cbmvax.UUCP (Randell Jesup)
Distribution: na
Organization: Commodore Technology, West Chester, PA
Lines: 34

In article <11234@steinmetz.ge.com> oconnor%sungod@steinmetz.UUCP writes:
>An article by jesup@cbmvax.UUCP (Randell Jesup) says:
>] >  Processor	    avg read	bus	bandwidth	 MB/s:MIPS
>] >		     latency   width   at the CPU   MIPS   ratio
>] 40 Mhz Rpm-40	      100ns	32+16   120 MB/s     33     ~4
>] 			       data inst	   native
>] 
>] 	If one is talking Vax Mips (which from the original msg we aren't):
>] 40 Mhz Rpm-40	      100ns	32+16   120 MB/s    14-16  ~8-9
>] 			       data inst	     vax

>How soon they forget :-). Correct figures for bandwidth of the RPM40
>are 160 MBytes/sec of data, and 80 MBytes/sec of instructions, for
>a total of 240 MB/s of AVAILABLE bandwidth.

	Oops.  So I can't count.  Corrected figures:

 40 Mhz Rpm-40	      100ns	32+16   240 MB/s     33     ~8
 			       data inst	   native
 
 	If one is talking Vax Mips (which from the original msg we aren't):
 40 Mhz Rpm-40	      100ns	32+16   240 MB/s    14-16  ~15
 			       data inst	     vax

Actually, the real numbers we want are for what it does with a fast cache, and
a slow memory bus beyond that.  Then measure the Mips/main memory bandwidth.
Of course, then we get into cache sizing problems...

>Hi Randell : got your mail, mail to you bounced. I'll try again.
> Dennis O'Connor   oconnor%sungod@steinmetz.UUCP  ARPA: OCONNORDM@ge-crd.arpa

Dennis:  Try uunet!cbmvax!jesup (or steinmetz!uunet!cbmvax!jesup)

Randell Jesup, Commodore Engineering {uunet|rutgers|ihnp4|allegra}!cbmvax!jesup