Path: utzoo!attcan!uunet!cbmvax!jesup
From: jesup@cbmvax.UUCP (Randell Jesup)
Newsgroups: comp.arch
Subject: Re: Maximum MIPS for a given memory bandwidth?
Message-ID: <4029@cbmvax.UUCP>
Date: 15 Jun 88 19:22:58 GMT
References: <6921@cit-vax.Caltech.Edu> <11234@steinmetz.ge.com> <4028@cbmvax.UUCP>
Reply-To: jesup@cbmvax.UUCP (Randell Jesup)
Distribution: na
Organization: Commodore Technology, West Chester, PA
Lines: 16

>In article <11234@steinmetz.ge.com> oconnor%sungod@steinmetz.UUCP writes:
>>How soon they forget :-). Correct figures for bandwidth of the RPM40
>>are 160 MBytes/sec of data, and 80 MBytes/sec of instructions, for
>>a total of 240 MB/s of AVAILABLE bandwidth.

	I did some thinking, and have a guess at actual average bandwidth
(VERY rough):  100% of instruction bandwidth + 30-40% data bandwidth ~= 140MB/s

 40 Mhz Rpm-40	      100ns	32+16   140 MB/s     33     ~4.5
 			       data inst  avg	   native
 
 	If one is talking Vax Mips (which from the original msg we aren't):
 40 Mhz Rpm-40	      100ns	32+16   140 MB/s    14-16  ~9-10
 			       data inst  avg	     vax

Randell Jesup, Commodore Engineering {uunet|rutgers|ihnp4|allegra}!cbmvax!jesup