Path: utzoo!attcan!uunet!lll-winken!lll-tis!helios.ee.lbl.gov!pasteur!ucbvax!amdcad!tim
From: tim@amdcad.AMD.COM (Tim Olson)
Newsgroups: comp.arch
Subject: Re: Maximum MIPS for a given memory bandwidth?
Message-ID: <22080@amdcad.AMD.COM>
Date: 16 Jun 88 02:33:43 GMT
References: <6921@cit-vax.Caltech.Edu> <22050@amdcad.AMD.COM> <291@wombat.UUCP> <22063@amdcad.AMD.COM> <292@wombat.UUCP>
Reply-To: tim@amdcad.UUCP (Tim Olson)
Distribution: na
Organization: Advanced Micro Devices
Lines: 18

In article <292@wombat.UUCP> george@wombat.UUCP (George Scolaro) writes:
| Does average bandwith tell more about the memory design? Output from
| the AMD29000 simulator (V4.21 PC) indicates that with 0 wait states
| the device attains 20.71 MIPS. With 1 wait state on every memory access
| the device attains 14.08 MIPS (Quote from Byte May 88). So, just 1 wait
| state impacts the performance quite dramatically.

That is true, it does if that wait-state is inserted into all
instruction requests.  I was thinking more along the lines of burst
mode: there are many schemes whereby we can supply an instruction per
cycle in burst mode, with some increased latency for starting the burst
access.  Video-DRAM designs, Static-column memories, interleaved DRAMS
are all examples.  These designs are usually much cheaper than
the single-cycle SRAM needed to provide peak bandwidth, which may not
even be required.

	-- Tim Olson
	Advanced Micro Devices
	(tim@delirun.amd.com)