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From: aglew@urbsdc.Urbana.Gould.COM
Newsgroups: comp.arch
Subject: Re: Maximum MIPS for a given memory ban
Message-ID: <28200162@urbsdc>
Date: 15 Jun 88 19:16:00 GMT
References: <6921@cit-vax.Caltech.Edu>
Lines: 23
Nf-ID: #R:cit-vax.Caltech.Edu:6921:urbsdc:28200162:000:921
Nf-From: urbsdc.Urbana.Gould.COM!aglew    Jun 15 14:16:00 1988


>>I am confused. How can a risc machine have a higher "vax mips" than
>>native mips? MORE (not less) risc instructions are required to
>>do the same task, when compared to a vax.
>
>Not always. Consider A=B+C, all in registers:
>    VAX:
>	mov rB,rA
>	add rC,rA
>    3 address RISC:
>	add rA,rB,rC
>
>So, we have an existence proof. What characteristics of the machine
>actually let this happen?

Well, I embarassed myself. If I'd said 68000 I could almost have
gotten away with it, but the VAX has 3 address instructions.

VAX is kind of the ultimate CISC (there could be a whole discussion
about this); the point I wanted to make was that number of CISC
instructions is not necessarily less than number of RISC instructions,
due to things like 3 address instructions and choice of operations.
The 88000 bit field instructions are a good example of the last
- simple enough for brute force implementation, but powerful.