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From: firth@sei.cmu.edu (Robert Firth)
Newsgroups: comp.arch
Subject: Re: Maximum MIPS for a given memory ban
Message-ID: <5884@aw.sei.cmu.edu>
Date: 16 Jun 88 13:07:14 GMT
References: <6921@cit-vax.Caltech.Edu> <28200161@urbsdc>
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In article <28200161@urbsdc> aglew@urbsdc.Urbana.Gould.COM writes:

))I am confused. How can a risc machine have a higher "vax mips" than
))native mips? MORE (not less) risc instructions are required to
))do the same task, when compared to a vax.
)
)Not always. Consider A=B+C, all in registers:
)    VAX:
)	mov rB,rA
)	add rC,rA
)    3 address RISC:
)	add rA,rB,rC
)
)So, we have an existence proof. What characteristics of the machine
)actually let this happen?

There are no VAX instructions called "mov" and "add".  Perhaps the
author meant to write

	MOVL  Rb,Ra
	ADDL2 Rc,Ra

But in any event, what he ought to have written is

	ADDL3 Rb,Rc,Ra

which, like the generic risc, is one instruction and 4 bytes.