Path: utzoo!attcan!uunet!pdn!alan
From: alan@pdn.UUCP (Alan Lovejoy)
Newsgroups: comp.arch
Subject: Re: Maximum MIPS for a given memory bandwidth?
Message-ID: <3488@pdn.UUCP>
Date: 16 Jun 88 14:25:32 GMT
References: <6921@cit-vax.Caltech.Edu> <22050@amdcad.AMD.COM> <291@wombat.UUCP> <22063@amdcad.AMD.COM> <6955@cit-vax.Caltech.Edu> <22081@amdcad.AMD.COM>
Reply-To: alan@pdn.UUCP (0000-Alan Lovejoy)
Distribution: na
Organization: Paradyne Corporation, Largo, Florida
Lines: 22

>In article <6955@cit-vax.Caltech.Edu> mangler@cit-vax.Caltech.Edu (Don Speck) writes:
>| So the table is amended as follows:
>| 
>|   Processor	    avg read	bus	bandwidth   VAX  MB/s:MIPS
>| 		     latency   width	available  "MIPS"  ratio
>| 25 MHz 88000	       45ns?   32+32	185 MB/s?    17     11?

Where did you get a 25 MHz 88000?  I believe all benchmark figures so
far are based on the 20 MHz part, including the 17 VUPS rating.

Motorola says that the pcc/88k compiler produces Dhrystone code that
runs 25,000 times/sec on the 20 MHz part, the Green Hills C/88k compiler
gets 34,000/sec, and Tadpole Technology claims 45,000/sec with their
compiler.  All at 20 MHz, but not necessarily with that same cache
sizes in the case of Tadpole.


-- 
Alan Lovejoy; alan@pdn; 813-530-8241; Paradyne Corporation: Largo, Florida.
Disclaimer: Do not confuse my views with the official views of Paradyne
            Corporation (regardless of how confusing those views may be).
Motto: Never put off to run-time what you can do at compile-time!